1. Field of the Invention
The invention relates to a method of manufacturing a thin film transistor (TFT) integrated circuit device, and more particularly, to a method of forming a tapered polysilicon profile in the manufacture of a thin film transistor integrated circuit device.
2. Description of the Prior Art
In the article, "A Stacked-CMOS Cell Technology for High-Density SRAM's,+ by Yasuhiro Uemoto, Eiji Fujii, Akira Nakamura, Kohji Senda, and Hiromitsu Takagi, IEEE Transactions on Electron Devices, Vol. 39, No. 10, October 1992, pp. 2359-2363, the authors discuss the use of a polysilicon thin film transistor (TFT). The authors show that the cell area of a stacked-CMOS cell can be greatly decreased by using a thin film transistor load in place of a conventional high resistive load. They describe a process for fabricating a TFT load with as large a polysilicon grain size as possible.
Referring to FIG. 1A, a TFT device is usually formed on an oxide substrate 1 followed by polycrystalline or amorphous silicon 2, CVD silicon oxide 3, and polycrystalline or amorphous silicon 4. A vertical rigid polysilicon etching profile 2 is used as the gate or the source/drain and channel of the bottom part of the TFT which results in a high electric field around the sharp corner 5 and poor CVD oxide quality around the sharp corner 5.
Referring now to FIG. 1B, the same TFT device has a tapered polysilicon etching profile 6 which serves as the gate or the source/drain and channel of the bottom part of the TFT. The smooth profile 6 without the sharp corners allows for a more even electrical field and more even step coverage of the CVD oxide 3.
U.S. Pat. Nos. 5,079,617 to Yoneda, 4,291,321 to Pfleiderer et al, 5,109,258 to Redwine, and 5,136,355 to Kerr et al each show tapered gate structures. All are formed by different means and for different reasons than that of the present invention. For example, Redwine forms his tapered gate by using thermal oxidation to convert to silicon oxide the polysilicon surrounding the masked planned gate area. One method used by Pfleiderer et al uses a silicon dioxide layer under a glasseous layer to form the gate. The glasseous layer is etched more than is the silicon dioxide layer resulting in a tapered profile. The glasseous layer is then melted to round the edges of the tapered profile.